1. Field of the Invention
This invention pertains to power semiconductors and in particular to a power metal oxide semiconductor field effect transistor (hereinafter referred to as power MOSFET) featuring improved ruggedness.
2. Description of Related Art
The power MOSFET features a high breakdown voltage and low on-resistance in DC mode and fast switching rate (i.e., low switching loss value) in AC mode. The on-resistance of the power MOSFET consists mainly of channel resistance, JFET resistance, accumulation resistance, and epitaxial resistance (a.k.a. drift resistance). Here, the epitaxial resistance comes to make up for majority of the on-resistance as the rated voltage increases. In addition, the power MOSFET requires greater breakdown voltage with an increase in rated voltage. The thickness and resistivity of the epitaxial layer must be increased in order to accommodate this, but an inevitable outcome of increasing the two factors is the concurrent increase of the epitaxial layer's on-resistance. The on-resistance value and the breakdown voltage value in a power MOSFET, therefore, form a trade-off relationship, and such relationship must be weighed heavily in designing power MOSFETs.
Residing inside the power MOSFET is an NPN parasitic bipolar transistor. Once initiated within the MOSFET, it is possible for the transistor to latch while in “on” state (Not MOSFET on, but NPN Tr is on) and ultimately destroy the power MOSFET. Therefore, it is crucial that the power MOSFET is rugged enough to counter the actions of the parasitic bipolar transistor. And the key to manufacturing such power MOSFET featuring high ruggedness is appropriate dispersion of the ruggedness current flowing within the power MOSFET. Here, ruggedness current refers to the current flowing through the diode (pn-junction diode) when reverse current is impressed on the power MOSFET.
FIG. 1(a) illustrates a power MOSFET (100) featuring the conventional closed patterned cell structure, whereas FIG. 1(b) illustrates a sectional view along line A-A′ in FIG. 1(a). The gap between the hexagonal cells in FIG. 1(a), which is the gate pitch corresponding to “d” in FIG. 1(a), is equidistant in order to yield greater channel density per surface area. The resolution capacity of photolithography devices must be considered, however, when designing the gate pitch because each of the cells must accommodate an n+ source area.
The following refers to FIG. 1(a) and FIG. 1(b) and describes a power MOSFET featuring the conventional hexagonal layout. An n− epitaxial area (130) is formed on top of an n+ drain area (120), where the thickness and resistance values of the n− epitaxial area (130) function as key factors in determining the actual breakdown voltage and on-resistance values of the power MOSFET. p− body areas (142) are formed in regular intervals on the n-epitaxial area (130). n+ source areas (160) are then formed on two internal ends of the p-body area (142), close the p− body area's (142) upper surface. p+ body areas (141) form within the p− body area (142), between the n+ source areas (160). Gate dielectrics (155) interpose over the p− body areas (142), n− epitaxial area (130), and n+ source areas (160) to form gate electrodes (150). A source electrode (180) and a n+ source areas (160) are formed on top of the p+ body area (141) and the n+ drain area (110) and underneath the n+ drain area (120). Formed on top of the gate electrodes (150) are PSG (phosphosilicate glass) layers (170) that isolate the gate electrodes (150) from the source electrodes (180).
The above-described power MOSFET features a hexagonal design for greater cell density and minimizes dead zones for lowered on-resistance. This design also increases the channel density per surface area, allowing for lower on-resistance than any other design.
The depletion layer in hexagonal power MOSFETs, however, take a spherical form when reverse voltage is impressed between the drain and source, causing the critical current density to geometrically concentrate on the spherical shape and lowering the breakdown voltage. In respect to alternating current properties, the hexagonal power MOSFET also performs at a low switching rate. The capacitance between the power MOSFET's gate electrode and the drain electrode (Cgd) determines its switching rate, where Cgd is determined by the epitaxial area covered by the gate electrodes between body areas. The greater the epitaxial layer coverage, the greater the Cgd, and this results in a decreased switching rate and greater heat radiation from the MOSFET. Ergo, gate electrodes in polygonal power MOSFETs inevitably cover a greater area of the epitaxial layer, resulting in increased Cgd and a lowered switching rate.
To resolve this problem inherent in the above-described hexagonal power MOSFET, a stripe cell-structured design was developed. This design is described below, in references to FIG. 2(a), FIG. 2(b), and FIG. 2(c). FIG. 2(a) illustrates a power MOSFET (100) featuring a striped cell configuration, whereas FIG. 2(b) illustrates a sectional view along line B-B′ in FIG. 2(a). As shown in the two diagrams, the striped power MOSFET (200) is very similar in design to the hexagonal power MOSFET (100) in FIG. 1(a) and FIG. 1(b), except that here the p+ body areas (241) and gate electrodes (250) are striped. The striped power MOSFET also consists of drain electrodes (210), n+ drain areas (220), n− epitaxial areas (230), p+ bodies (241), p− bodies (242), gate electrodes (250), gate dielectrics (255), n+ source areas (260), and source electrodes (280). FIG. 2(c) illustrates the relationship between the p+ body areas (241) and the p-type edge area (244) in a striped power MOSFET. In a normal striped power MOSFET, the p+ areas are comprised of striped p+ body areas (241) that are surrounded by a p-type edge area (244). Both ends of the p+ body areas (241) are attached to the p-type edge area (244), which is fabricated as a single unit.
With a striped configuration, the above-described power MOSFET can effectively resolve the problem associated with hexagonal power MOSFETs by offering improved breakdown voltage and switching rate.
The power MOSFET shown in FIG. 2(a) through (c), however, is still problematic in that electrical current flows mainly through the p+ body areas. Current then concentrates on those areas to activate the parasitic bipolar transistor and ultimately destroys the power MOSFET.
Accordingly, as discussed above, the prior art still has some drawbacks that could be improved. The present invention aims to resolve the drawbacks in the prior art.